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Package Design for Signal Integrity of LPDDR

My role
First author (M.S. thesis) — design parameter study, 3D EM simulation, and signal integrity analysis
Objective
Reduce the multiple reflections caused by impedance mismatched segments—bonding wire, trace, and solder ball—in the DQ channel of an LPDDR memory package, improving signal integrity as the data rate increases.
Approach
Modifying the bonding wire & reference plane structures and the prepreg dielectric constant mitigates the impedance mismatch.
Outcome
M.S. Thesis
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